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Registrations open – Free VLSI Workshop on 24th June 2018

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Website www.maven-silicon.com | Edit Freely

Category

Deadline: June 23, 2018 | Date: June 24, 2018

Venue/Country: Bangalore, India

Updated: 2018-04-04 21:21:38 (GMT+9)

Call For Papers - CFP

Find the answer of all your questions regarding Semiconductor Industry at the FREE VLSI workshop happening on 24th June with , CEO- Maven Silicon & Founder- Aceic Design Technologies With 20+ years’ Experience in Semiconductor Industry

.

Who can attend?

Pre-Final/Final Year Students of B.Tech /B.E. from ECE, EEE,TE, Instrumentation

Students of ME/MTech/MS in Electronics/MSc Electronics

Students who have finished engineering from any of the above stream in 2016/2017

Date: 24/06/2018, Sunday

Time: 9 AM to 12.30 PM

Speaker: Mr.P R SivaKumar, CEO Maven Silicon

Agenda of the workshop

Overview of VLSI Design

IP, Chips and SoCs

Introduction to VLSI Design Flow

Front End Vs Back End

RTL Design using HDL

Verilog Vs VHDL, Overview of Verilog

Functional Verification

System Verilog and UVM based test benches

Code and Functional coverage

Indian Semiconductor Industry

Products and road maps, Job Opportunities, VLSI Finishing school

Q &A Session

Register here:

Please register only at the above link. Once you register, you will receive a confirmation call from us. Post confirmation, the admit card will be generated and sent to your registered email ID. In Case, you don’t receive the confirmation call, please call us on 9845016248/7338454291

Highlights of the Workshop:

1. Knowledge sharing by veteran trainer Mr. Sivakumar (CEO - Maven Silicon) with experience of 20+ years in VLSI industry.

2. Scholarship coupon worth of Rs. 5000/-

3. Participation Certificate

Note:

Entry to the workshop is FREE.

Only candidates with admit card will be allowed.

Limited seats available.

Snacks will be provided.

We look forward to welcoming you!!


Keywords: Accepted papers list. Acceptance Rate. EI Compendex. Engineering Index. ISTP index. ISI index. Impact Factor.
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